Reference is made to U.S. Pat. No. 5,999,417 (the '417 patent), the contents of which are hereby incorporated in this document.
The figures of the '417 patent depict power circuit topologies that have isolation stages. Some of these isolation stages are current-fed (for example, through an inductor as shown in FIG. 6A), and others are voltage-fed (for example, from a capacitor as shown in FIG. 6B). In addition, the examples of isolation stages depicted in the '417 patent also have the characteristic that the effective DC voltage seen at the input to an isolation stage (for example, the DC voltage, VB, across capacitor CB in FIGS. 6A and 6B) is the output voltage multiplied by a transformer's primary/secondary turns ratio (assuming we ignore resistive drops). Furthermore, because a transformer is operated at about a 50% duty cycle, the primary side switches of the isolation stages depicted in the '417 patent are stressed to approximately 2VB when they are off. (The actual voltage is slightly higher to insure that the transformer resets before the beginning of the next cycle.)
The '417 patent is not limited to these specific isolation stage topologies. Other topologies that exhibit the invention of that patent are also possible.